Semiconductor fabrication techniques have seen substantial advancements in recent years, permitting large amounts of digital circuitry to be used in cost-effective ways. These advancements, coupled with recent innovations in the design and architecture of data processing systems, have resulted in computing system architectures that are structured in various ways to be fault-tolerant. One such fault-tolerant architecture involves, for example, mating circuitry (e.g., a central processing unit) with substantially identical circuitry (e.g., another central processing unit), and operating both in "lock-step", using the same data and instruction signals to produce processed data. The processed data of one is checked against that of the other to ensure proper operation. Typically, only one of the circuits is responsible for performing system functions; the other operates only to produce (hopefully) substantially identical check data. U.S. Pat. Nos. 4,358,823, 4,785,453, and 4,843,608 illustrate various techniques for operating pairs of processor units or identically structural circuitry in such self-checking modes.
While these various self-checking schemes using pairs (or multiple pairs) of similarly structured circuitry, such as those illustrated in the above-identified patents, are capable of performing their intended self-checking functions, they are not without limitation. For example, operating in lock-step fashion requires careful management and attention to such design characteristics as clock-skew. Data inputs to the individual circuits (e.g., processor units), when obtained from the same source, must be applied and accepted on the proper state transitions of the clock signals that operate both circuits for credible self-checking operation. The same is true for data output signals, particularly those that are used for comparison. In addition, for proper system operation, it is often required that buffering (using, for example, clocked registers) be used to temporarily store data for application to other elements such as, for example, comparator circuitry, in order to maintain the self-checking capability. Data buffering may also be needed when tri-state busses are used to separate input data from output data. All of these characteristics tend to have an impact on cycle time of the operation of the circuitry, add extra components (e.g., memory, etc.), and can operate to extend data paths to external circuitry in order to account, for example, for a slow "master" processor units as compared with a faster "slave" or check processor units caused, among other things, by the speed of component parts and/or relative clock phase.
On the market today are microprocessor units capable of being operated at very high clock speeds (e.g., the R3000 RISC microprocessor manufactured by MIPS Computers, Incorporated of Santa Clara, Calif., which can operate at a 50 MHz clock rate). Attempts to incorporate such high speed microprocessors into the self-checking designs discussed above not only exacerbate the problems described, but create new problems. For the most part, it is very difficult, if not impossible, to operate at these very high clock speeds. In short, present self-checking architectures can severely limit system operating speed.
Accordingly, it is evident that there is a need for apparatus providing comparison between high speed synchronous circuitry for self-checking capability, in real time, and with minimum delay. Preferably, the self-checking capability should provide minimum timing impact to the compared device or circuitry.